[syn: complex instruction set computing, complex instruction set computer, CISC]
WordNet (r) 3.0 (2006):
CISC
    n 1: an agency of the Canadian government that unifies the
         intelligence units of Canadian law enforcement agencies
         [syn: Criminal Intelligence Services of Canada, CISC]
    2: (computer science) a kind of computer architecture that has a
       large number of instructions hard coded into the CPU chip
       [syn: complex instruction set computing, complex
       instruction set computer, CISC] [ant: RISC, reduced
       instruction set computer, reduced instruction set
       computing]
V.E.R.A. -- Virtual Entity of Relevant Acronyms (February 2016):
CISC
       Complex Instruction Set Computer (CPU)
The Free On-line Dictionary of Computing (30 December 2018):
Complex Instruction Set Computer
CISC
   (CISC) A processor where each instruction can perform several
   low-level operations such as memory access, arithmetic
   operations or address calculations.  The term was coined in
   contrast to Reduced Instruction Set Computer.
   Before the first RISC processors were designed, many computer
   architects were trying to bridge the "semantic gap" - to
   design instruction sets to support high-level languages by
   providing "high-level" instructions such as procedure call and
   return, loop instructions such as "decrement and branch if
   non-zero" and complex addressing modes to allow data
   structure and array accesses to be compiled into single
   instructions.
   While these architectures achieved their aim of allowing
   high-level language constructs to be expressed in fewer
   instructions, it was observed that they did not always result
   in improved performance.  For example, on one processor it was
   discovered that it was possible to improve the performance by
   NOT using the procedure call instruction but using a sequence
   of simpler instructions instead.  Furthermore, the more
   complex the instruction set, the greater the overhead of
   decoding an instruction, both in execution time and silicon
   area.  This is particularly true for processors which used
   microcode to decode the (macro) instruction.  It is easier
   to debug a complex instruction set implemented in microcode
   than one whose decoding is "hard-wired" in silicon.
   Examples of CISC processors are the Motorola 680x0 family
   and the Intel 80186 through Intel 486 and Pentium.
   (1994-10-10)