The Free On-line Dictionary of Computing (30 December 2018):

instruction scheduling

    The compiler phase that orders instructions
   on a pipelined, superscalar, or VLIW architecture so as
   to maximise the number of function units operating in parallel
   and to minimise the time they spend waiting for each other.

   Examples are filling a delay slot; interspersing
   floating-point instructions with integer instructions to
   keep both units operating; making adjacent instructions
   independent, e.g. one which writes a register and another which
   reads from it; separating memory writes to avoid filling the
   write buffer.

   Norman P. Jouppi and David W. Wall, "Available
   Instruction-Level Parallelism for Superscalar and
   Superpipelined Processors"

(ftp://gatekeeper.dec.com/archive/pub/DEC/WRL/research-reports/WRL-TR-89.7.ps.Z),
   Proceedings of the Third International Conference on
   Architectural Support for Programming Languages and Operating
   Systems, pp. 272--282, 1989.

   [The SPARC Architecture Manual, v8, ISBN 0-13-825001-4]